An on-chip bus provides communications among microprocessors, input/output devices and on-chip devices on an integrated circuit. Current on-chip bus standards are either proprietary, complex, or both. The complexity is caused in part by restrictive input/output requirements chosen to meet all anticipated needs. Each master device on the on-chip bus must be designed to account for all anticipated forms of transfers with various slave devices. Other factors contributing to the complexity are timing requirements that do not synchronize signals to clock edges. Consequently, master and slave devices attached to the on-chip bus must include circuitry that determines when input signals become valid.